1. Field of the Invention
The present invention, generally, relates to testing integrated circuits and similar devices. More specifically, the invention relates to scan-based testing, debugging and diagnosis of integrated circuits, printed circuit boards, and systems on a chip.
2. Background Art
Scan-based testing is frequently employed during the development and manufacturing of electronic components (e.g., Integrated Circuits (ICs)) and systems (e.g., Printed Circuit Boards (PCBs) and Systems On a Chip (SoC) for detecting and diagnosing defects and for debugging. This test method is commonly referred to as “scan” because the state elements of the circuits are configured to form a serial shift (i.e., scan) register, often called a scan path or scan chain, during a test mode of operation. A scan test typically involves serially shifting data into (scan-in) and out of (scan-out) the scan path(s) of a Unit Under Test (UUT) as a way of applying digital logic values as test stimulus and capturing digital logic values in response to the test stimulus. The responses are normally compared against expected scan out data, and any failure during the data comparison generally indicates detection of a defect in the UUT. Thus, for a digital circuit, the scan test mode provides full controllability and observability of inputs and outputs of combinational logic included in the UUT. This greatly simplifies the test problem and provides for high quality tests with overall reduced costs.
Providing serial scan access enables “visibility” into a UUT for test and debug purposes by providing a way of observing/controlling the circuit states without the need for physical probing. Without scan, internal nodes of the circuit would only be accessible through the physical pins of the UUT. In this case, any testing or debugging of the circuit would require applying complex sequences of operations to provide control/observation of the internal states. A UUT with scan can also be used to access other circuits connected to the UUT, e.g., circuits embedded within the UUT such as embedded memories and cores or other circuits connected externally to the UUT. This approach is often employed to access external memories for the purpose of programming their contents, e.g., programming FLASH memory from the Boundary Scan path of an IC connected to the FLASH memory.
Scan access is typically performed in accordance with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture specification, which is incorporated herein by reference. This standard was developed primarily to solve the problems of PCB testing. The IEEE 1149.1 Standard utilizes a Boundary Scan path to facilitate access to the I/O pins of devices mounted on the PCB. In addition, the IEEE 1149.1 Standard can be used to access scan paths within an IC to facilitate test, debug, and in-system configuration of ICs, PCBs, and systems.
FIG. 1 illustrates the conventional IEEE 1149.1 Boundary Scan Architecture 100. As shown in FIG. 1, an IC compliant with the IEEE 1149.1 Boundary Scan Architecture 100 has four (optionally, five) additional component pins called Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO) (and optionally Test Reset (TRSTN)). These dedicated test pins are commonly referred to as the Test Access Port (TAP). Additionally, IEEE 1149.1 compliant ICs implement three scan registers—an Instruction Register (IR) 102 and two standard Data Registers (DRs) called a Bypass Register 104 and a Boundary Scan Register (BSR) 106. FIG. 1 also shows a User DR 108, which the IEEE 1149.1 Standard permits designers to implement to support additional test and debug features in the architecture 100 such as internal scan paths and Built-In Self-Test (BIST).
In the IEEE 1149.1 Standard, the five TAP pins have the following functions:
TCK is an input signal that is provided to synchronize the execution of various test actions, both within the individual IC components and among multiple IC components being accessed through the TAP. TCK is a periodic clock signal, which is generally free running with a constant frequency. However, TCK may be started or stopped, or its frequency may be changed, depending on the application. Most test actions take place on the rising-edge of the TCK pulse but certain actions occur only on the falling-edge of TCK.
TMS is an input pin that is used to control the internal state of a TAP Controller 110 (see FIG. 1). The TAP Controller 110 is a 16-state Finite State Machine (FSM) that provides a standard IEEE 1149.1 protocol for accessing functions within the architecture 100. Certain actions defined by the IEEE 1149.1 Standard are permitted, and can be executed, only in specific TAP Controller states. TMS values are sampled on the rising-edge of TCK.
TRSTN is an input signal that provides asynchronous reset of the TAP Controller 110, which brings it into the Test-Logic-Reset state to allow the IC component to execute its mission function. Regardless of the state of the TCK and TMS inputs, the target TAP Controller enters and remains in the Test-Logic-Reset state as long as TRSTN is at a logic value of 0. Since it is also possible to reset the TAP Controller 110 by setting TMS to the logic 1 value for at least 5 TCK periods, TRSTN has been defined as an optional input signal.
TDI is an input signal that provides serial scan-in data to the device. TDI receives test data from another device's TDO, or from an external test resource such as a scan controller or Automatic Test Equipment (ATE). The logic value of the signal on TDI is sampled on the rising-edge of TCK.
TDO is the serial scan-out from the device. When a device is enabled to scan data, its TDO transmits test data to another device's TDO, or back to the test apparatus. Scan-out values on the TDO output change with the falling-edge of TCK.
The IEEE 1149.1 Standard facilitates connecting the TAP ports of multiple components together to form an IEEE 1149.1 bus, which allows the connected circuits to be accessed with a common TAP protocol. This is typically achieved by connecting the serial data terminals, TDI and TDO, of the individual devices in a daisy chain fashion such that the TDO output from the previous device along the chain is connected to the TDI input of the next device in the chain. Then, by connecting all of the individual TMS, TCK (and optionally TRSTN) signals of the devices in common, an overall TAP bus is formed.
Conventional test procedures may not be adequate in an application environment. For example, the deep submicron technologies are prone to exhibit defects as functional failures, because existing test environments lack in emulation of the application environment. The high density of gates packed in deep submicron technologies require complex fault models to emulate the application environment. The VLSI and ULSI era are not sufficiently equipped in in-system diagnostics and in-system test in the event of functional failure in the application environment. Hence there is a need to address this issue by proposing a method for in-system diagnostics and test in application environment.